1. Field of the Invention
This invention relates to processors and, more particularly, to optimizing functional units shared within processors.
2. Description of the Related Art
In some processor implementations, several different functional units may be provided to process different types of instructions or operations. For example, an integer execution unit may be configured to execute integer-type instructions, and a floating-point execution unit may be configured to execute floating-point instructions. In some embodiments, additional types of functional units may be provided for different purposes. Further, in some embodiments, certain functional units may be more tightly coupled to an instruction fetch pipeline than others; for example, a given functional unit may be logically implemented as a free-running coprocessor largely independent of instruction issue logic, or as part of a fixed pipeline whose operation is closely coordinated with instruction issue logic.
Depending on how instructions or operations are partitioned among functional units, different functional units may implement instructions or operations that are similar in nature. For example, multiplication instructions may be defined for both integer and floating-point operations. However, implementing separate execution resources for similar types of instructions may be costly, depending on the function. For example, hardware multipliers may require substantial die area, particularly as the width of the multiplier increases. Further, depending on the workload presented by executing software, in certain circumstances the separate execution resources may be poorly utilized, exacerbating the area cost of providing those resources.